Satellite operators are offering increasingly sophisticated on-board processing capabilities necessitating the use of the latest ultra‑deep‑submicron FPGAs and ASICs. These have demanding, low-voltage, high-current, power requirements and OEMs are being challenged to offer more functionality from smaller payloads and platforms. Cost and time-to-market are also key drivers!

Relatively, smaller satellites harvest less energy and with operators increasingly using faster and more on-board processing, there is a requirement that as much of the possible power budget is available for the payload. Traditional power-distribution architectures comprising an isolated DC-DC to step-down the external bus input, followed by localized POLs to produce the required load voltages, are becoming too inefficient because of large I²R drops. To deliver the next generation of New Space missions, improvements are needed in conversion loss, power density, physical size and a transient response compatible with the switching speeds of the latest ultra‑deep‑submicron devices.

Instead of the conventional, intermediate power-distribution comprising an isolated DC‑DC followed by buck bricks, Vicor Corporation’s patented Factorized Power Architecture (FPA™) uses a modular approach to minimize I²R distribution losses, maximize efficiency and improve transient response.

The FPA comprises two stages: voltage regulation followed by transformation. First, a buck-boost topology is used to generate a 48V intermediate rail from an external source, which is significantly higher than the lower legacy buses typically input to POLs. For example, a 48V output bus requires four times less current than a 12V intermediate bus for the same power (P = VI ) and PDN losses are the square of the current (P = I²R ), which reduces by sixteen. Placing a regulator first to produce 48V achieves the highest efficiency, allowing smaller satellites to avail of more of the harvested energy.

The second stage of the FPA uses a transformer to convert the 48V intermediate rail to the desired load voltage, e.g. 1V. The output is a fixed fraction of the input (K-factor) defined by the turns ratio. Stepping down the voltage increases the current by the same amount, e.g. a 1A input current would be multiplied to an output of 48A:

A Pre-Regulation Module (PRM™) and a Voltage-Transformation Module (VTM™) current multiplier combine to realize the FPA, with each device fulfilling its specialized role to enable complete DC-DC conversion. The PRM generates a regulated ‘factorized bus’ from an unregulated input followed by the VTM, which transforms (steps down) the 48V to the desired load voltage.

The VTM’s high bandwidth avoids the need for large point-of-load capacitance. Even without any external output capacitors, the output of a VTM exhibits a limited voltage perturbation in response to a sudden power surge. A minimal amount of external bypass capacitance (in the form of low ESR/ESL ceramic capacitors) is sufficient to eliminate any transient voltage overshoot. Without imposing the bandwidth limitations of an internal control loop struggling to maintain regulation, the VTM offers a unique capacitance‑multiplication feature. For example, the effective, shunt output capacitance is 2304 times the input capacitance when a K factor of 1/48 is used, i.e. C_SEC = C_PRI * K². This means that significantly less decoupling is needed downstream of the VTM and only a small amount of capacitance at its input offers the same energy storage as the bulky tantalums typically added to the 1V output of a traditional buck brick as illustrated in Figure 1.

Low impedance is a key requirement for powering low-voltage, high current loads efficiently and the use of a VTM also reduces the effective resistance seen from the secondary side by K². This allows the VTM to be placed at the load, either laterally or vertically, resulting in a lower-loss PDN. The FPA's lower-current, higher-voltage intermediate bus means that the PRM can be located physically away from the VTM without impacting efficiency. This gives you more flexibility when deciding where to place the PRM, less worries about area congestion at the load and more freedom to size power planes for maximum current density. This floor-planning is very different to the traditional brick approach, which requires the isolated DC-DC and POLs to be close together to minimize I²R distribution losses.

Present space-grade, isolated DC-DCs and buck POLs are PWM-based devices with the output power proportional to the duty cycle of the switching frequency. These hard‑switched converters use a square wave to drive an inductor or transformer with the MOSFET dissipating energy as it is turned on and off. A square wave contains lots of harmonics that must be filtered or they will conduct or radiate throughout the system. The VTM’s topology uses a sinusoidal current in the primary winding, producing a cleaner output noise spectrum requiring less filtering. Existing space-qualified buck regulators and forward/flyback DC-DCs specify efficiencies in the range of 67 – 95% and 47 – 87% respectively.

Today, there are 12 suppliers of space-grade switching POLs offering almost 30 non‑isolated convertors. Input voltages range from 3 to 16V, load voltages and currents from 0.785 to 9.6V and 4 to 18A respectively, with switching frequencies from 100kHz to 1MHz. Previously, I described the theory of conversion for the buck topology, what criteria to consider when selecting space-qualified parts, and how to choose values for the inductor, input, and output capacitance.

There are seven vendors of space-qualified isolating DC-DCs offering over 30 families of parts generating single, double, or triple standard voltages, or in some cases, adjustable, regulated, stepped-down intermediate outputs. Power ratings range from 2.5 to 500W. Previously, I described the theory of conversion for the forward and flyback topologies.

To meet the power-distribution and low-voltage, high-current needs of future NewSpace constellations, Vicor is qualifying its novel, Sine Amplitude Converter (SAC™) topology for space applications. This patented, ZCS/ZVS technology offers higher efficiencies, larger power densities, and lower EMI emissions than existing space-grade DC-DCs. SAC is a transformer-based, series-resonant, forward architecture that operates at a fixed frequency equal to the resonance of a primary tank circuit as shown in Figure 2.

To highlight the superior densities offered by the new rad-tolerant DC‑DCs, Figures 4 and 5 compare their relative sizes with existing space-grade switching POLs and isolated DC‑DCs respectively. The power density of each convertor in W/in³, its efficiency in % and current density in A/in², have been annotated in blue, orange, and red respectively. A range of efficiencies are typically specified for different load conditions and the maximum values from each datasheet are displayed below.

The new, rad-tolerant, COTS SAC DC-DCs are an innovative and enabling technology for NewSpace applications. When compared with existing qualified converters, they deliver major increases in output power, density, and efficiency in a smaller volume and lighter form-factor. Regulated voltages are significantly cleaner with less bulk decoupling. Parts will have heritage from next year and evaluation boards are available to help you de-risk future mission needs.

The FPA is a major advance to reduce the I²R distribution losses handicapping existing intermediate power architectures. A low-current, factorized bus allows much more freedom to place the BCM® and PRM away from the typically-congested load area.

A modular, 100V PDN solution now exists offering SWaP benefits to supply the latest, ultra-deep-submicron, space-grade semiconductors. The VTMs provide high-performing ratiometric DC-DCs and when combined with a PRM, enable a complete closed-loop FPA exploiting the efficiency advantages of a high-voltage factorized bus (Figure 6).